1. Technical Field
The present disclosure relates to synchronization circuits and methods and, more particularly, to synchronization circuits and methods for phase synchronization of output signals of two level shifters irrespective of variations in circuit manufacturing processes and the power supply voltages applied to the level shifters.
2. Discussion of the Related Art
FIG. 1 is a schematic diagram of a conventional circuit 100 for generating first and second level-shifted signals CLK_out1 and CLK_out2 from a reference signal CLK_in. Referring to FIG. 1, the circuit 100 includes a buffer 110 and a level shifting block 120. The buffer 110 improves the driving capability of the reference signal CLK_in and outputs the reference signal CLK_in. A second power supply voltage VDD and a third power supply voltage VSS are applied to the buffer 110. Accordingly, the maximum and minimum voltages between which the signal output from the buffer 110 swings are the second and third power supply voltages VDD and VSS.
The level shifting block 120 includes two level shifters 121 and 122. The first level shifter 121 receives the output signal from the buffer 110 and generates the first level-shifted signal CLK_out1 swinging between a first power supply voltage VGH and the third power supply voltage VSS. The first power supply voltage VGH is higher than the second power supply voltage VDD.
The second level shifter 122 receives the output signal from the buffer 110 and generates the second level-shifted signal CLK_out2 swinging between the second power supply voltage VDD and a fourth power supply voltage VGL. The fourth power supply voltage VGL is lower than the third power supply voltage VSS.
FIG. 2 is a circuit diagram of the first level shifter 121, and FIG. 3 is a circuit diagram of the second level shifter 122. The first and second level shifters 121 and 122 shown in FIGS. 2 and 3, respectively, include a plurality of NMOS transistors and PMOS transistors. The on-off behavior of the NMOS and PMOS transistors is controlled by their threshold voltages. The threshold voltages can vary according to variations in circuit manufacturing processes. The variations in the threshold voltages change the electrical characteristics of the level shifters. In particular, delay or offset voltages of the first and second level-shifted signals output from the level shifters 121 and 122 relative to the input signals of the level shifters 121 and 122 may be increased. The first and second level shifters 121 and 122 are widely used so that further explanation thereof is omitted.
FIG. 4 is a waveform diagram of the input and output signals of the circuit 100 for generating the level-shifted signals shown in FIG. 1. Referring to FIG. 4, the swing voltage of the reference signal CLK_in is V1, the swing voltage of the first level-shifted signal CLK_out1 is V2, and the swing voltage of the second level-shifted signal CLK_out2 is V3. The swing voltage V1 corresponds to the difference between the second power supply voltage VDD and the third power supply voltage VSS. The swing voltage V2 corresponds to the difference between the first power supply voltage VGH and the third power supply voltage VSS. The swing voltage V3 corresponds to the difference between the second power supply voltage VDD and the fourth power supply voltage VGL. Therefore, the swing voltages V1, V2 and V3 are at different voltages.
A delay d11 of the first level-shifted signal CLK_out1 generated using the reference signal CLK_in is different from a delay d12 of the second level-shifted signal CLK_out2 generated using the reference signal CLK_in.
The respective swing voltages V1, V2 and V3 are different because differing power supply voltages are applied to the buffer 110 and the first and second level shifters 121 and 122. Furthermore, the delay d11 differs from the delay d12 due to the different internal circuits of the first and second level shifters 121 and 122, the layout positions of the first and second level shifters 121 and 122 and variations in process parameters. The variations in process parameters are a result of a process variation of the PMOS and NMOS transistors. The variation in threshold voltage becomes a chief cause of the difference between the delay d11 of the first level-shifted signal CLK_out1 and the delay d12 of the second level-shifted signal CLK_out2.
The systems employing the circuit of FIG. 1 use the first and second level-shifted signals CLK_out1 and CLK_out2 output from the circuit on the assumption that the first and second level-shifted signals CLK_out1 and CLK_out2 have different voltages and the same phase. However, the operation of the system may be unstable due to the aforementioned phase discord.